This invention relates to a switchable load for testing a semiconductor integrated circuit device.
Frequently the specifications for a semiconductor integrated circuit device define performance of the device by reference to a pin, when operating as an output, being connected through a specified resistive load to a specified voltage. It would be desirable in testing of an integrated circuit device to be able to load an output pin of the device under test (DUT) in this manner, but the value of the specified load resistance can vary widely from device to device, and it may be specified with a high degree of precision. A suitable resistive load could be realized by arranging fixed resistors in a relay-switched resistor network, allowing a single resistor to be selected for a given test, but since the value of the resistance can vary widely, a large number of resistors would be required. It has not been economical to provide a load of this nature because of the considerable space occupied by the resistors and the power consumed in controlling the switches. In addition, the load resistor must be out of circuit in a test cycle in which the pin operates as an input to the DUT, which requires that a low resistance switch be inserted in series between the relay-switched resistor network and the DUT pin and that the switch be operated very rapidly, typically in less than 100 ns.
One compromise solution to the problem of providing the proper resistive load has employed a diode bridge connected to a programmable current source, in which the DUT output provides the commutating voltage for the diode switches. This approach is subject to disadvantage because it does not provide a resistive termination for the interconnect cable to the DUT and only meets the specified load conditions at two voltage-current points. Other solutions have been to provide a third voltage level to which the test system driver could be switched. This typically would provide a fixed 50 ohm value of load resistance, and the switching time could be controlled by the driver I/O timing. This solution offers only one value of load resistance and typically does not test the DUT at its specified load conditions.